WireDAQ — Architecture Simulator

Data Flownodes → transport → collector → dashboard

Offered Load

—

Link Util

—

Packet Loss

—

Buffer

—

Latency

—

Sync Error

—

Throughput—

End-to-End Latency—

Buffer Occupancy—

Packet Loss Rate—

Synchronization Error — per node clock drift—

Sensor Streamslive channels

A——

Util

—

Loss

—

Buffer

—

Latency

—

B——

Util

—

Loss

—

Buffer

—

Latency

—

Throughput

End-to-End Latency

Buffer Occupancy

Packet Loss Rate

Architecture Comparison — A vs B

Metric	Config A	Config B

WireDAQ architecture simulator · finite buffers, modeled jitter & loss, independent node clocks · Space run/pause · R reset · C compare
Illustrative model — the contract is packet_schema.yaml + golden vectors · 24-byte header + 2-byte CRC, int16 samples