WireDAQ

Wire-ready data-acquisition architecture simulator

Design the architecture before you wire the hardware.

Flight Avionics Data Acquisition Hexagonal Architecture Hardware-in-the-Loop Python · C · C++ · Rust
Open the Console View the Roadmap
WireDAQ — wire-ready DAQ architecture simulator

About

Flight avionics is distributed data acquisition under hostile constraints. WireDAQ builds the integration seams and an honest simulator first, in pure software, with a single wire contract that the firmware and ground software both meet — so the hardware drops into a system that already works.

Three codecs — Python, C firmware, and C++ — are held byte-for-byte to committed golden vectors, and loss, reorder, line noise, CRC failures, and clock drift are modeled from day one, not discovered at flight. A real sensor board drops in behind the same port; advancing a phase is a wiring change, not a rewrite.

Run it yourself: pip install wiredaq, then wiredaq-slice — or open the interactive tools below, right in your browser. Source and docs live on GitHub.

Interactive Tools

How much

Capacity Console

A live capacity / what-if simulator: finite buffers, modeled loss and jitter, independent per-node clocks, A/B comparison, and report export — matching the packet schema.

Open the console
Why

5-Phase Roadmap

Step through the five integration phases and watch real hardware grow inward from both ends while the wire contract holds still.

Open the roadmap

Both tools are self-contained — no server, no build step.

Why WireDAQ

One enforced contract

Three codecs — Python, C firmware, C++ — held byte-for-byte to committed golden vectors.

Honest fakes

Loss, reorder, line noise, CRC, and clock drift modeled from day one — not discovered at flight.

Ports & adapters

A real sensor board drops in behind the same port; advancing a phase is a wiring change, not a rewrite.

Latest Release

Now on PyPIv0.3.0

Install with pip install wiredaq — no checkout needed

  • Per-node clock reconstruction (ADR 0002) — the ground station recovers each node's drift and aligns differently-drifting nodes onto one timeline; wiredaq-clocksync demos it and the CSV export gains a reconstructed t_ref_us column.
  • Rust/Lua backend now simulates the link — seeded loss / jitter / reorder with a decode-side receiver, plus executed faults / assertions; its golden vectors are read from the shared vectors.json and gated in CI.
  • Correctness hardening — heartbeat handling fixed end-to-end, control-plane frames validated fail-closed across Python / C / Rust, and clock drift now modelled honestly.
  • Continuous integration — tests on Python 3.10–3.12 plus cross-language C / C++ / Rust codec conformance on every push.
Full release notes