WireDAQ
Flight avionics is distributed data acquisition under hostile constraints. WireDAQ builds the integration seams and an honest simulator first, in pure software, with a single wire contract that the firmware and ground software both meet — so the hardware drops into a system that already works. The two tools below are the interactive front-ends; open them right in your browser.
Capacity Console →
A live capacity / what-if simulator: finite buffers, modeled loss and jitter, independent per-node clocks, A/B comparison, and report export — matching the packet schema.
5-Phase Roadmap →
Step through the five integration phases and watch real hardware grow inward from both ends while the wire contract holds still.
Both tools are self-contained — no server, no build step.
One enforced contract
Three codecs — Python, C firmware, C++ — held byte-for-byte to committed golden vectors.
Honest fakes
Loss, reorder, line noise, CRC, and clock drift modeled from day one — not discovered at flight.
Ports & adapters
A real sensor board drops in behind the same port; advancing a phase is a wiring change, not a rewrite.
Now on PyPI
Install with pip install wiredaq — no checkout needed.
- Per-node clock reconstruction (ADR 0002) — the ground station recovers each node's drift and aligns differently-drifting nodes onto one timeline;
wiredaq-clocksyncdemos it and the CSV export gains a reconstructedt_ref_uscolumn. - Rust/Lua backend now simulates the link — seeded loss / jitter / reorder with a decode-side receiver, plus executed
faults/assertions; its golden vectors are read from the sharedvectors.jsonand gated in CI. - Correctness hardening — heartbeat handling fixed end-to-end, control-plane frames validated fail-closed across Python / C / Rust, and clock drift now modelled honestly.
- Continuous integration — tests on Python 3.10–3.12 plus cross-language C / C++ / Rust codec conformance on every push.